Dual-VT SRAM cells with full-swing single-ended bit line sensing for high-performance on-chip cache in 0.13 μm technology generation

Authors:
Fatih Hamzaoglu;Yibin Te;Ali Keshavarzi;Kevin Zhang;Siva Narendra;Shekhar Borkar;Mircea Stan;Vivek De
Affiliations:
Microprocessor Research Labs, Intel Corporation, Hillsboro, OR;Microprocessor Research Labs, Intel Corporation, Hillsboro, OR;Microprocessor Research Labs, Intel Corporation, Hillsboro, OR;Low Power Design Lab, Intel Corporation, Hillsboro, OR;Microprocessor Research Labs, Intel Corporation, Hillsboro, OR;Microprocessor Research Labs, Intel Corporation, Hillsboro, OR;Department of ECE, University of Virginia, Charlottesville, VA;Microprocessor Research Labs, Intel Corporation, Hillsboro, OR
Venue:
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Year:
2000

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Abstract

Comparisons among different dual-VT design choices for a large on-chip cache with single-ended sensing show that the design using a dual-VT cell and low-VT peripheral circuits is the best, and provides 10% performance gain with 1.2x larger active leakage power, and 1.6% larger cell area compared to the best design using high-VT cells.