Design limitations in deep sub-0.1&mgr;m CMOS SRAM

Authors:
Robert K. Grube;Qi Wang;Sung-Mo Kang
Affiliations:
University of California, Santa Cruz, CA;University of California, Santa Cruz, CA;University of California, Santa Cruz, CA
Venue:
Proceedings of the 12th ACM Great Lakes symposium on VLSI
Year:
2002

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Abstract

Leakage effects in deep sub-0.1&mgr;m CMOS technologies are of critical concern to designers of high-performance integrated circuits. Recent estimates [1] of a 7.5x increase in leakage current per chip generation; along with several proposals for energy-efficient cache architectures that unfortunately do not address static leakage-energy issues [2], [3], [4], have heightened concerns over the functionality and stability of future high-performance SRAM cache designs. Each of these future technology generations, in addition to having increased short-channel effects (SCEs) will now also suffer from gate leakage currents across physically and electrically thin (1.5nm) SiO2 gate dielectrics. In this paper we demonstrate the limits of this scaling on the operational behavior of on-chip SRAM cache designs, and briefly discuss the impact of these results on high-performance memory architectures.