IBM Journal of Research and Development - Special issue: terrestrial cosmic rays and soft errors
DRG-cache: a data retention gated-ground cache for low power
Proceedings of the 39th annual Design Automation Conference
Drowsy caches: simple techniques for reducing leakage power
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Low-leakage asymmetric-cell SRAM
Proceedings of the 2002 international symposium on Low power electronics and design
Managing leakage for transient data: decay and quasi-static 4T memory cells
Proceedings of the 2002 international symposium on Low power electronics and design
Performance, energy, and reliability tradeoffs in replicating hot cache lines
Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems
Enhancing data cache reliability by the addition of a small fully-associative replication cache
Proceedings of the 18th annual international conference on Supercomputing
Soft error and energy consumption interactions: a data cache perspective
Proceedings of the 2004 international symposium on Low power electronics and design
Analyzing heap error behavior in embedded JVM environments
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Replication Cache: A Small Fully Associative Cache to Improve Data Cache Reliability
IEEE Transactions on Computers
Improving soft-error tolerance of FPGA configuration bits
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Low-leakage robust SRAM cell design for sub-100nm technologies
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Combined time and information redundancy for SEU-tolerance in energy-efficient real-time systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Evaluating instruction cache vulnerability to transient errors
MEDEA '06 Proceedings of the 2006 workshop on MEmory performance: DEaling with Applications, systems and architectures
Modeling and improving data cache reliability: 1
Proceedings of the 2007 ACM SIGMETRICS international conference on Measurement and modeling of computer systems
Evaluating instruction cache vulnerability to transient errors
ACM SIGARCH Computer Architecture News
Case study of reliability-aware and low-power design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Recruiting Decay for Dynamic Power Reduction in Set-Associative Caches
Transactions on High-Performance Embedded Architectures and Compilers II
Applying decay to reduce dynamic power in set-associative caches
HiPEAC'07 Proceedings of the 2nd international conference on High performance embedded architectures and compilers
Improving chip multiprocessor reliability through code replication
Computers and Electrical Engineering
IEEE Transactions on Circuits and Systems Part I: Regular Papers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Reducing leakage power and improving the reliability ofdata stored in the memory cells are both becomingchallenging as technology scales down. While the smallerthreshold voltages causes increased leakage, smallersupply voltages and node capacitances can be a problemfor soft errors. This work compares the soft error rates ofsome recently proposed SRAM leakage optimizationapproaches. Our results using designs in 70nmtechnology show that many of these approaches mayincrease the soft error rates as compared to a standard6T SRAM. Further, we demonstrate that there is atradeoff between optimizing the leakage power andimproving the immunity to soft error.