Advanced compiler design and implementation
Advanced compiler design and implementation
Area efficient architectures for information integrity in cache memories
ISCA '99 Proceedings of the 26th annual international symposium on Computer architecture
Dead-block prediction & dead-block correlating prefetchers
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
Cache decay: exploiting generational behavior to reduce cache leakage power
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
Drowsy caches: simple techniques for reducing leakage power
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Timekeeping in the memory system: predicting and optimizing memory behavior
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Power4 System Design for High Reliability
IEEE Micro
Soft Error Sensitivity Characterization for Microprocessor Dependability Enhancement Strategy
DSN '02 Proceedings of the 2002 International Conference on Dependable Systems and Networks
A 1.3GHz fifth generation SPARC64 microprocessor
Proceedings of the 40th annual Design Automation Conference
Analyzing Soft Errors in Leakage Optimized SRAM Design
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Characterizing the Effects of Transient Faults on a High-Performance Processor Pipeline
DSN '04 Proceedings of the 2004 International Conference on Dependable Systems and Networks
The Soft Error Problem: An Architectural Perspective
HPCA '05 Proceedings of the 11th International Symposium on High-Performance Computer Architecture
Computing Architectural Vulnerability Factors for Address-Based Structures
Proceedings of the 32nd annual international symposium on Computer Architecture
Balancing Performance and Reliability in the Memory Hierarchy
ISPASS '05 Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2005
| Hi-index | 0.00 |
Recent research shows that microprocessors are increasingly susceptible to transient errors. In order to protect microprocessors cost-effectively, the first step is to accurately understand the impact of transient errors on the system reliability. While many research efforts have been focused on studying the vulnerability of data caches and other on-chip hardware components, instruction caches have received less attention. However, instructions are read every cycle, any undetected or uncorrected soft errors in instructions can lead to erroneous computation, wrong control flow or system crash.This paper studies the instruction cache vulnerability by considering both the raw SRAM rate and the cache vulnerability factor. Based on the concept of cache vulnerability factor, we also investigate the impact of different cache configuration parameters on the reliability of instruction caches. We find that on average 67.5% of instruction cache soft errors can be masked by the I-cache itself without impacting other system components. While quantifying the instruction cache vulnerability itself does not solve the reliability problem of instruction cache against transient errors, we believe this work can provide useful insights for designers to develop cost-effective solutions to protect I-caches and to optimally balance the reliability of instruction caches with other system goals, such as cost, performance and energy.