Techniques to Reduce the Soft Error Rate of a High-Performance Microprocessor
Proceedings of the 31st annual international symposium on Computer architecture
The Case for Lifetime Reliability-Aware Microprocessors
Proceedings of the 31st annual international symposium on Computer architecture
Logic soft errors in sub-65nm technologies design and CAD challenges
Proceedings of the 42nd annual Design Automation Conference
Design and Evaluation of Hybrid Fault-Detection Systems
Proceedings of the 32nd annual international symposium on Computer Architecture
Recursive TMR: Scaling Fault Tolerance in the Nanoscale Era
IEEE Design & Test
Compiler-guided register reliability improvement against soft errors
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Deployment of Better Than Worst-Case Design: Solutions and Needs
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
uComplexity: Estimating Processor Design Effort
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Fault Tolerance Techniques for the Merrimac Streaming Supercomputer
SC '05 Proceedings of the 2005 ACM/IEEE conference on Supercomputing
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Interconnect and Thermal-aware Floorplanning for 3D Microprocessors
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A Simulation-Based Soft Error Estimation Methodology for Computer Systems
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SEED: scalable, efficient enforcement of dependences
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Evaluating instruction cache vulnerability to transient errors
MEDEA '06 Proceedings of the 2006 workshop on MEmory performance: DEaling with Applications, systems and architectures
Cost-efficient soft error protection for embedded microprocessors
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Architecting a reliable CMP switch architecture
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Energy management for real-time embedded systems with reliability requirements
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Examining ACE analysis reliability estimates using fault-injection
Proceedings of the 34th annual international symposium on Computer architecture
Compiler-Managed Software-based Redundant Multi-Threading for Transient Fault Detection
Proceedings of the International Symposium on Code Generation and Optimization
Modeling and improving data cache reliability: 1
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Transient fault prediction based on anomalies in processor events
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Verification-guided soft error resilience
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Study of the Effects of SEU-Induced Faults on a Pipeline Protected Microprocessor
IEEE Transactions on Computers
Evaluating instruction cache vulnerability to transient errors
ACM SIGARCH Computer Architecture News
Proceedings of the 13th international conference on Architectural support for programming languages and operating systems
Hierarchical Verification for Increasing Performance in Reliable Processors
Journal of Electronic Testing: Theory and Applications
Online Estimation of Architectural Vulnerability Factor for Soft Errors
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
IFRA: instruction footprint recording and analysis for post-silicon bug localization in processors
Proceedings of the 45th annual Design Automation Conference
A Systematic Approach to Automatically Generate Multiple Semantically Equivalent Program Versions
Ada-Europe '08 Proceedings of the 13th Ada-Europe international conference on Reliable Software Technologies
Soft-error resilience of the IBM POWER6 processor
IBM Journal of Research and Development
A framework for estimating NBTI degradation of microarchitectural components
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Sequential element design with built-in soft error resilience
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Architecture Design for Soft Errors
Architecture Design for Soft Errors
Towards scalable reliability frameworks for error prone CMPs
CASES '09 Proceedings of the 2009 international conference on Compilers, architecture, and synthesis for embedded systems
Hardware authentication leveraging performance limits in detailed simulations and emulations
Proceedings of the 46th Annual Design Automation Conference
Post-silicon bug localization for processors using IFRA
Communications of the ACM
International Journal of Parallel Programming
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Shoestring: probabilistic soft error reliability on the cheap
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Impact analysis of performance faults in modern microprocessors
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Analysis of single-event effects in embedded processors for non-uniform fault tolerant design
IIT'09 Proceedings of the 6th international conference on Innovations in information technology
Necromancer: enhancing system throughput by animating dead cores
Proceedings of the 37th annual international symposium on Computer architecture
Modeling soft errors for data caches and alleviating their effects on data reliability
Microprocessors & Microsystems
Reliability-aware dynamic energy management in dependable embedded real-time systems
ACM Transactions on Embedded Computing Systems (TECS)
MICRO '43 Proceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture
Post-silicon bug detection for variation induced electrical bugs
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Proceedings of the 38th annual international symposium on Computer architecture
Releasing efficient beta cores to market early
Proceedings of the 38th annual international symposium on Computer architecture
Assuring application-level correctness against soft errors
Proceedings of the International Conference on Computer-Aided Design
Scaling probabilistic timing verification of hardware using abstractions in design source code
Proceedings of the International Conference on Formal Methods in Computer-Aided Design
Efficient soft error protection for commodity embedded microprocessors using profile information
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A first-order mechanistic model for architectural vulnerability factor
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Fast online error detection and correction with thread signature calculae
Microprocessors & Microsystems
Reducing NBTI-induced processor wearout by exploiting the timing slack of instructions
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Dynamic code duplication with vulnerability awareness for soft error detection on VLIW architectures
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Low cost control flow protection using abstract control signatures
Proceedings of the 14th ACM SIGPLAN/SIGBED conference on Languages, compilers and tools for embedded systems
CEP: Correlated Error Propagation for Hierarchical Soft Error Analysis
Journal of Electronic Testing: Theory and Applications
Quantitative evaluation of soft error injection techniques for robust system design
Proceedings of the 50th Annual Design Automation Conference
Formal performance analysis for faulty MIMO hardware
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Physical-defect modeling and optimization for fault-insertion test
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IVF: characterizing the vulnerability of microprocessor structures to intermittent faults
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On the Impact of Performance Faults in Modern Microprocessors
Journal of Electronic Testing: Theory and Applications
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The progression of implementation technologies into thesub-100 nanometer lithographies renew the importance ofunderstanding and protecting against single-event upsets indigital systems.In this work, the effects of transient faults onhigh performance microprocessors is explored.To perform athorough exploration, a highly detailed register transfer levelmodel of a deeply pipelined, out-of-order microprocessor wascreated.Using fault injection, we determined that fewer than15% of single bit corruptions in processor state result in softwarevisible errors.These failures were analyzed to identifythe most vulnerable portions of the processor, which werethen protected using simple low-overhead techniques.Thisresulted in a 75% reduction in failures.Building upon thefailure modes seen in the microarchitecture, fault injectionsinto software were performed to investigate the level of maskingthat the software layer provides.Together, the baselinemicroarchitectural substrate and software mask more than 9out of 10 transient faults from affecting correct program execution.