System Dependability Evaluation via a Fault List Generation Algorithm
IEEE Transactions on Computers
DEPEND: A Simulation-Based Environment for System Level Dependability Analysis
IEEE Transactions on Computers
Introduction to Linear Optimization
Introduction to Linear Optimization
Fault Injection and Dependability Evaluation of Fault-Tolerant Systems
IEEE Transactions on Computers
Impact of Deep Submicron Technology on Dependability of VLSI Circuits
DSN '02 Proceedings of the 2002 International Conference on Dependable Systems and Networks
Characterizing the Effects of Transient Faults on a High-Performance Processor Pipeline
DSN '04 Proceedings of the 2004 International Conference on Dependable Systems and Networks
Simulation Based System Level Fault Insertion Using Co-verification Tools
ITC '04 Proceedings of the International Test Conference on International Test Conference
Test set enrichment using a probabilistic fault model and the theory of output deviations
Proceedings of the conference on Design, automation and test in Europe: Proceedings
RT-Level Deviation-Based Grading of Functional Test Sequences
VTS '09 Proceedings of the 2009 27th IEEE VLSI Test Symposium
Fault injection boundary scan design for verification of fault tolerant systems
ITC'94 Proceedings of the 1994 international conference on Test
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Hardware fault insertion is a promising method for system reliability assessment and fault isolation. It provides feed-back on the fault tolerance of a large system, creates artificial faulty scenarios that can be used as reference points for fault diagnosis, and leads to a quality diagnostic program. Optimization of fault insertion location is critical for accelerating the assessment of system reliability and constructing a complete knowledge base for fault diagnosis. In this work, we construct a pin-level fault model that is able to effectively mimic the errors (effects) caused by physical defects within the component. A simulation framework and optimization techniques are proposed to select a minimum subset of output pins that can represent as many physical defects as possible. The optimization results provide guidelines on the fault insertion locations and the appropriate fault types for insertion. In addition, three intrinsic characteristics of output pins, including testability number, fan-in size, and transition counts, are analyzed. The effectiveness of the proposed model is evaluated in terms of impact on system response and error-detection latency. Experimental results are presented for OpenCore benchmarks.