Simulation Based System Level Fault Insertion Using Co-verification Tools

Authors:
Bill Eklow;Anoosh Hosseini;Chi Khuong;Shyam Pullela;Toai Vo;Hien Chau
Affiliations:
Cisco Systems Inc., San Jose CA,;Cisco Systems Inc., San Jose CA,;Cisco Systems Inc., San Jose CA,;Cisco Systems Inc., San Jose CA;Cisco Systems Inc., San Jose CA;Cisco Systems Inc., San Jose CA
Venue:
ITC '04 Proceedings of the International Test Conference on International Test Conference
Year:
2004

Citing 0
Cited 2

Statistically translating low-level error probabilities to increase the accuracy and efficiency of reliability simulations in hardware description languages

Proceedings of the 18th ACM Great Lakes symposium on VLSI
Physical-defect modeling and optimization for fault-insertion test

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

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Abstract

This paper presents a simulation-based, fault insertion environment, which allows faults to be "injected" into a Verilog model of the hardware. A co-verification platform is used to allow real, system level software to be executed in the simulation environment. A fault manager is used to keep track of the faults that are inserted on to the hardware and to monitor diagnostic messages to determine whether the software is able to detect, diagnose and/or cope with the injected fault. Examples will be provided to demonstrate the capabilities of this approach as well as the resource requirements (time, system, human). Other benefits and issues of this approach will also be discussed.