Fault injection boundary scan design for verification of fault tolerant systems

  • Authors:

  • Savio Chau

  • Affiliations:

  • Jet Propulsion Laboratory

  • Venue:
  • ITC'94 Proceedings of the 1994 international conference on Test
  • Year:
  • 1994

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Abstract

In this paper, we propose a design technique called the Fault Injection Boundary Scan (FIBS) for fault injection that is much more eflcient than the traditional hardwired pin-level fault injection. The FIBS augments the boundary scan design to facilitate the injection of faults to the input and output pins of a VLSI chip. In addition to the capabilities of a conventional boundary scan design, the FIBS can interpret the test vector contained in the boundary scan cells as markers for fault-injected pins during fault injection. The compatibility of the FIBS with the boundary scan also promises relatively small overhead.