Universal fault simulation using fault tuples
Proceedings of the 37th Annual Design Automation Conference
Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic
DSN '02 Proceedings of the 2002 International Conference on Dependable Systems and Networks
A Diagnostic ATPG for Delay Faults Based on Genetic Algorithms
Proceedings of the IEEE International Test Conference on Test and Design Validity
Pattern Sensitivity: A Property to Guide Test Generation for Combinational Circuits
ATS '99 Proceedings of the 8th Asian Test Symposium
CMOS Electronics: How It Works, How It Fails
CMOS Electronics: How It Works, How It Fails
Delay Fault Testing of Core-Based Systems-on-a-Chip
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Logic Circuits Testing for Transient Faults
ETS '05 Proceedings of the 10th IEEE European Symposium on Test
Fully parallel stochastic computation architecture
IEEE Transactions on Signal Processing
A system architecture solution for unreliable nanoelectronic devices
IEEE Transactions on Nanotechnology
Probabilistic maximum error modeling for unreliable logic circuits
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Journal of Electronic Testing: Theory and Applications
Physical-defect modeling and optimization for fault-insertion test
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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We present a probabilistic fault model that allows any number of gates in an integrated circuit to fail probabilistically. Tests for this fault model, determined using the theory of output deviations, can be used to supplement tests for classical fault models, thereby increasing test quality and reducing the probability of test escape. Output deviations can also be used for test selection, whereby the most effective test patterns can be selected from large test sets during time-constrained and high-volume production testing. Experimental results are presented to evaluate the effectiveness of patterns with high output deviations for the single stuck-at and bridging fault models.