EST: The new frontier in automatic test-pattern generation
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Dynamic search-space pruning techniques in path sensitization
DAC '94 Proceedings of the 31st annual Design Automation Conference
Rapid diagnostic fault simulation of stuck-at faults in sequential circuits using compact lists
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
GRASP: A Search Algorithm for Propositional Satisfiability
IEEE Transactions on Computers
Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
Efficient conflict driven learning in a boolean satisfiability solver
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
RT-Level ITC'99 Benchmarks and First ATPG Results
IEEE Design & Test
Diagnostic Fault Equivalence Identification Using Redundancy Information and Structural Analysis
Proceedings of the IEEE International Test Conference on Test and Design Validity
A diagnostic test generation procedure for synchronous sequential circuits based on test elimination
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A Diagnostic Test Generation Procedure for Combinational Circuits Based on Test Elimination
ATS '98 Proceedings of the 7th Asian Test Symposium
Diagnostic Test Pattern Generation for Sequential Circuits
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
20.2 New Techniques for Deterministic Test Pattern Generation
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Diagnosis oriented test pattern generation
EURO-DAC '90 Proceedings of the conference on European design automation
Test set enrichment using a probabilistic fault model and the theory of output deviations
Proceedings of the conference on Design, automation and test in Europe: Proceedings
ATS '06 Proceedings of the 15th Asian Test Symposium
VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)
VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)
An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits
IEEE Transactions on Computers
On capture power-aware test data compression for scan-based testing
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Deviation-based LFSR reseeding for test-data compression
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Diagnosis of automata failures: a calculus and a method
IBM Journal of Research and Development
Generation of compact test sets with high defect coverage
Proceedings of the Conference on Design, Automation and Test in Europe
QC-fill: an X-fill method for quick-and-cool scan test
Proceedings of the Conference on Design, Automation and Test in Europe
Robust Boolean reasoning for equivalence checking and functional property verification
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test-Quality/Cost Optimization Using Output-Deviation-Based Reordering of Test Patterns
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Silicon Diagnosis is the process of locating potential defect sites (candidates) in a defective chip. These candidates are then used as an aid during physical failure analysis. It is desired that the cardinality of the candidate set returned by silicon diagnosis be as small as possible. To this end, effective test patterns that can distinguish as many fault-pairs in the candidate set are critical. Generation of such diagnostic patterns is referred to as Automatic Diagnostic Test Generation (ADTG). In this paper, we propose an aggressive and efficient learning framework for such a diagnostic test generation engine. It allows us to identify and prune non-trivial redundant search states thereby allowing to easily solve hard to distinguish or hard to prove equivalent fault-pairs. Further, we propose an incremental flow for ADTG, where the information learned during detection-oriented test generation is passed to and incrementally used by ADTG. Finally, we propose an interesting output deviation based X-filling of detection test patterns with the objective of enhancing test set's diagnostic ability. Experimental results on full-scan versions of ISCAS89/ITC99 circuits indicate that our incremental learning framework achieves up to 2脳 speed-up and/or resolves more initially unresolved fault-pairs for most circuits. Also, results indicate that the proposed X-filling method has the potential to distinguish more fault-pairs than the random X-filling method.