Test set enrichment using a probabilistic fault model and the theory of output deviations
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Probabilistic transfer matrices in symbolic reliability analysis of logic circuits
ACM Transactions on Design Automation of Electronic Systems (TODAES)
An improved soft-error rate measurement technique
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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An unified gate-level fault model for interconnect opens and bridges is proposed. Defects are modeled as constrained multiple line stuck-at faults. A novel feature of the proposed fault model is its flexibility to accommodate increasing levels of accuracy. ...