Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Introduction to Algorithms
Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic
DSN '02 Proceedings of the 2002 International Conference on Dependable Systems and Networks
Logic Circuits Testing for Transient Faults
ETS '05 Proceedings of the 10th IEEE European Symposium on Test
Design of Adaptive Nanometer Digital Systems for Effective Control of Soft Error Tolerance
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
A soft error rate analysis (SERA) methodology
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
FASER: Fast Analysis of Soft Error Susceptibility for Cell-Based Designs
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
MARS-C: modeling and reduction of soft errors in combinational circuits
Proceedings of the 43rd annual Design Automation Conference
On Accelerating Soft-Error Detection by Targeted Pattern Generation
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
Accelerating Soft Error Rate Testing Through Pattern Selection
IOLTS '07 Proceedings of the 13th IEEE International On-Line Testing Symposium
On Derating Soft Error Probability Based on Strength Filtering
IOLTS '07 Proceedings of the 13th IEEE International On-Line Testing Symposium
Multiple Fault Detection in Combinational Networks
IEEE Transactions on Computers
On ATPG for multiple aggressor crosstalk faults
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Soft error modeling and remediation techniques in ASIC designs
Microelectronics Journal
MICRO '43 Proceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture
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Soft errors caused by ionizing radiation have emerged as a major concern for current generation of CMOS technologies, and the trend is expected to get worse. The measurement unit for failures due to soft errors is failure in time (FIT) that represents the number of failures encountered per billion hours of device operation. FIT rate measurement is time consuming and calls for accelerated testing. To improve effectiveness of soft-error rate (SER) testing, the patterns must be targeted toward detecting node failures that are most likely. In this paper, we present a technique for identifying soft-error-susceptible sites based on efficient electrical analysis that treats soft errors as Boolean errors but uses analog strengths to decide whether such errors can propagate to the next stage. Next, we present pattern generation techniques for manifestable soft errors such that each pattern targets a maximal set of soft errors. These patterns maximize the likelihood of detecting a soft error when it occurs. The pattern generators target scan architecture. It is well known that scan test time is dominated by scan shifts, when no useful testing is being done. To improve efficiency of scan-based testing, we extend the functionality of the existing built-in logic block observation (BILBO) architecture to support test-per-clock operation. Such targeted pattern generation and test application improve SER characterization time by an order of magnitude.