IBM Journal of Research and Development - Special issue: terrestrial cosmic rays and soft errors
Soft-error Monte Carlo modeling program, SEMM
IBM Journal of Research and Development - Special issue: terrestrial cosmic rays and soft errors
Critical charge calculations for a bipolar SRAM array
IBM Journal of Research and Development - Special issue: terrestrial cosmic rays and soft errors
Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic
DSN '02 Proceedings of the 2002 International Conference on Dependable Systems and Networks
Logic soft errors in sub-65nm technologies design and CAD challenges
Proceedings of the 42nd annual Design Automation Conference
Logic SER Reduction through Flipflop Redesign
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
FASER: Fast Analysis of Soft Error Susceptibility for Cell-Based Designs
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
An efficient static algorithm for computing the soft error rates of combinational circuits
Proceedings of the conference on Design, automation and test in Europe: Proceedings
MARS-C: modeling and reduction of soft errors in combinational circuits
Proceedings of the 43rd annual Design Automation Conference
Energy-efficient soft error-tolerant digital signal processing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Soft error derating computation in sequential circuits
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Soft error reduction in combinational logic using gate resizing and flipflop selection
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Probabilistic transfer matrices in symbolic reliability analysis of logic circuits
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Tracking Uncertainty with Probabilistic Logic Circuit Testing
IEEE Design & Test
Enhancing design robustness with reliability-aware resynthesis and logic simulation
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
On the role of timing masking in reliable logic circuit design
Proceedings of the 45th annual Design Automation Conference
Case study of reliability-aware and low-power design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Sequential element design with built-in soft error resilience
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Architecture Design for Soft Errors
Architecture Design for Soft Errors
Circuit optimization techniques to mitigate the effects of soft errors in combinational logic
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Signature-based SER analysis and design of logic circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Reliability analysis of logic circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An improved soft-error rate measurement technique
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On soft error rate analysis of scaled CMOS designs: a statistical perspective
Proceedings of the 2009 International Conference on Computer-Aided Design
Cost aware fault tolerant logic synthesis in presence of soft errors
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Formal modeling and reasoning for reliability analysis
Proceedings of the 47th Design Automation Conference
Soft error modeling and remediation techniques in ASIC designs
Microelectronics Journal
A resilience roadmap: (invited paper)
Proceedings of the Conference on Design, Automation and Test in Europe
A timing-aware probabilistic model for single-event-upset analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analysis and optimization of nanometer CMOS circuits for soft-error tolerance
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design sensitivity of single event transients in scaled logic circuits
Proceedings of the 48th Design Automation Conference
Statistical Soft Error Rate (SSER) Analysis for Scaled CMOS Designs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
CARROT: a tool for fast and accurate soft error rate estimation
SAMOS'06 Proceedings of the 6th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
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We present a soft error rate analysis (SERA) methodology for combinational and memory circuits. SERA is based on a modeling and analysis-based approach that employs a judicious mix of probability theory, circuit simulation, graph theory and fault simulation. SERA achieves five orders of magnitude speed-up over Monte Carlo based simulation approaches with less than 5% error. Dependence of soft error rate (SER) of combinational circuits on supply voltage, clock period, latching window, circuit topology, and input vector values are explicitly captured and studied for a typical 0.18 /spl mu/m CMOS process. Results show that the SER of logic is a much stronger function of timing parameters than the supply voltage. Also, an "SER peaking" phenomenon in multipliers is observed where the center bits have an SER that is in order of magnitude greater than that of LSBs and MSBs.