Cost aware fault tolerant logic synthesis in presence of soft errors

Authors:
Xin He;Afshin Abdollahi
Affiliations:
University of California, Riverside, Riverside, CA, USA;University of California, Riverside, Riverside, CA, USA
Venue:
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Year:
2010

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Abstract

With the emergence of sub-100 nanometers, soft error failure rates (SER) due to Single-event Upsets (SEU) from particle strikes become unacceptable for combinational logic circuits. Triple modular redundancy (TMR) is applied to improve the reliability of VLSI circuits, entailing additional cost (area, delay, power consumption, e.g.). This paper introduce a partial TMR solution to optimize the area of fault tolerant VLSI circuits with SER constraints, presenting a novel optimization method by Binary Integer Linear Programming (BILP) with components consideration,. It also proposes an efficient SER evaluation model base on linear gate error propagation. A series of simulation on NCMC'89 benchmark is made. The experiment results show that this technique improves reliability by an average 57.95% with only 36.98% area overhead.