Soft-error Monte Carlo modeling program, SEMM
IBM Journal of Research and Development - Special issue: terrestrial cosmic rays and soft errors
Critical charge calculations for a bipolar SRAM array
IBM Journal of Research and Development - Special issue: terrestrial cosmic rays and soft errors
Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic
DSN '02 Proceedings of the 2002 International Conference on Dependable Systems and Networks
Logic soft errors in sub-65nm technologies design and CAD challenges
Proceedings of the 42nd annual Design Automation Conference
Soft Errors in Advanced Computer Systems
IEEE Design & Test
Cost-effective radiation hardening technique for combinational logic
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
A soft error rate analysis (SERA) methodology
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Analytical modeling of crosstalk noise waveforms using Weibull function
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Logic SER Reduction through Flipflop Redesign
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Soft error reduction in combinational logic using gate resizing and flipflop selection
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Enhancing design robustness with reliability-aware resynthesis and logic simulation
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
On the role of timing masking in reliable logic circuit design
Proceedings of the 45th annual Design Automation Conference
Guiding circuit level fault-tolerance design with statistical methods
Proceedings of the conference on Design, automation and test in Europe
Integration, the VLSI Journal
Adopting the Drowsy Technique for Instruction Caches: A Soft Error Perspective
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Signature-based SER analysis and design of logic circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On soft error rate analysis of scaled CMOS designs: a statistical perspective
Proceedings of the 2009 International Conference on Computer-Aided Design
Formal modeling and reasoning for reliability analysis
Proceedings of the 47th Design Automation Conference
Multiple transient faults in combinational and sequential circuits: a systematic approach
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
Radiation-induced Soft Errors: A Chip-level Modeling Perspective
Foundations and Trends in Electronic Design Automation
Statistical Soft Error Rate (SSER) Analysis for Scaled CMOS Designs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
CEP: Correlated Error Propagation for Hierarchical Soft Error Analysis
Journal of Electronic Testing: Theory and Applications
Retiming for Soft Error Minimization Under Error-Latching Window Constraints
Proceedings of the Conference on Design, Automation and Test in Europe
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Soft errors have emerged as an important reliability challenge for nanoscale VLSI designs. In this paper, we present a fast and efficient soft error rate (SER) computation algorithm for combinational circuits. We first present a novel parametric waveform model based on the Weibull function to represent particle strikes at individual nodes in the circuit. We then describe the construction of the SET descriptor that efficiently captures the correlation between the transient waveforms and their associated rate distribution functions. The proposed algorithm consists of operations to inject, propagate and merge SET descriptors while traversing forward along the gates in a circuit. The parameterized waveforms enable an efficient static approach to calculate the SER of a circuit. We exercise the proposed approach on a wide variety of combinational circuits and observe that our algorithm has linear runtime with the size of the circuit. The runtimes for soft error estimation were observed to be in the order of about one second, compared to several minutes or even hours for previously proposed methods.