A two moment RC delay metric for performance optimization
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Can recursive bisection alone produce routable placements?
Proceedings of the 37th Annual Design Automation Conference
Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic
DSN '02 Proceedings of the 2002 International Conference on Dependable Systems and Networks
Time Redundancy Based Soft-Error Tolerance to Rescue Nanometer Technologies
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Partial Error Masking to Reduce Soft Error Failure Rate in Logic Circuits
DFT '03 Proceedings of the 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Fast and accurate rectilinear steiner minimal tree algorithm for VLSI design
Proceedings of the 2005 international symposium on Physical design
A soft error rate analysis (SERA) methodology
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
FASER: Fast Analysis of Soft Error Susceptibility for Cell-Based Designs
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
An efficient static algorithm for computing the soft error rates of combinational circuits
Proceedings of the conference on Design, automation and test in Europe: Proceedings
MARS-C: modeling and reduction of soft errors in combinational circuits
Proceedings of the 43rd annual Design Automation Conference
Soft error reduction in combinational logic using gate resizing and flipflop selection
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Accurate and scalable reliability analysis of logic circuits
Proceedings of the conference on Design, automation and test in Europe
Node Mergers in the Presence of Don't Cares
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Enhancing design robustness with reliability-aware resynthesis and logic simulation
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Gate sizing to radiation harden combinational logic
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Circuit optimization techniques to mitigate the effects of soft errors in combinational logic
ACM Transactions on Design Automation of Electronic Systems (TODAES)
On soft error rate analysis of scaled CMOS designs: a statistical perspective
Proceedings of the 2009 International Conference on Computer-Aided Design
Formal modeling and reasoning for reliability analysis
Proceedings of the 47th Design Automation Conference
Clock skew scheduling for soft-error-tolerant sequential circuits
Proceedings of the Conference on Design, Automation and Test in Europe
Design as you see FIT: system-level soft error analysis of sequential circuits
Proceedings of the Conference on Design, Automation and Test in Europe
Statistical Soft Error Rate (SSER) Analysis for Scaled CMOS Designs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Retiming for Soft Error Minimization Under Error-Latching Window Constraints
Proceedings of the Conference on Design, Automation and Test in Europe
A low-cost, systematic methodology for soft error robustness of logic circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Soft errors, once only of concern in memories, are beginning to affect logic as well. Determining the soft error rate (SER) of a combinational circuit involves three main masking mechanisms: logic, timing and electrical. Most previous papers focus on logic and electrical masking. Here, we develop static and statistical analysis techniques to estimate timing masking through the error-latching window of each gate. Our SER analysis algorithms incorporating timing masking are 10--100x faster than comparable evaluators and can be used in synthesis and layout. We show that 62% of gates identified as error-critical using timing masking would not be identifiable by considering only logic masking. Furthermore, hardening the top 10% of error-critical gates leads to a 43% reduction in the SER. We also propose to decrease the error-latching window of each gate by relocating it such that path lengths to primary outputs are equalized. Our results show that this technique yields 14% improvement in SER with no area overhead.