IEEE Transactions on Computers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic
DSN '02 Proceedings of the 2002 International Conference on Dependable Systems and Networks
Soft Errors in Advanced Computer Systems
IEEE Design & Test
Logic SER Reduction through Flipflop Redesign
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Soft error rate analysis for sequential circuits
Proceedings of the conference on Design, automation and test in Europe
Enhancing design robustness with reliability-aware resynthesis and logic simulation
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
On the role of timing masking in reliable logic circuit design
Proceedings of the 45th annual Design Automation Conference
A systematic approach to modeling and analysis of transient faults in logic circuits
ISQED '09 Proceedings of the 2009 10th International Symposium on Quality of Electronic Design
Sequential element design with built-in soft error resilience
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analysis and optimization of nanometer CMOS circuits for soft-error tolerance
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Gate sizing to radiation harden combinational logic
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Retiming for Soft Error Minimization Under Error-Latching Window Constraints
Proceedings of the Conference on Design, Automation and Test in Europe
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Soft errors have been a critical reliability concern in nano-scale integrated circuits, especially in sequential circuits where a latched error can be propagated for multiple clock cycles and affect more than one output, more than once. This paper presents an analytical methodology for enhancing the soft error tolerance of sequential circuits. By using clock skew scheduling, we propose to minimize the probability of unwanted transient pulses being latched and also prevent latched errors from propagating through sequential circuits repeatedly. The overall methodology is formulated as a piecewise linear programming problem whose optimal solution can be found by existing mixed integer linear programming solvers. Experiments reveal that 30--40% reduction in the soft error rate for a wide range of benchmarks can be achieved.