Power estimation methods for sequential logic circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IBM experiments in soft fails in computer electronics (1978–1994)
IBM Journal of Research and Development - Special issue: terrestrial cosmic rays and soft errors
Logical effort: designing fast CMOS circuits
Logical effort: designing fast CMOS circuits
Trace-driven steady-state probability estimation in FSMs with application to power estimation
Proceedings of the conference on Design, automation and test in Europe
Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic
DSN '02 Proceedings of the 2002 International Conference on Dependable Systems and Networks
Soft Errors in Advanced Computer Systems
IEEE Design & Test
Soft Error Modeling and Protection for Sequential Elements
DFT '05 Proceedings of the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
MARS-C: modeling and reduction of soft errors in combinational circuits
Proceedings of the 43rd annual Design Automation Conference
Markovian analysis of large finite state machines
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Soft error vulnerability of iterative linear algebra methods
Proceedings of the 22nd annual international conference on Supercomputing
Process variability-aware transient fault modeling and analysis
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Circuit optimization techniques to mitigate the effects of soft errors in combinational logic
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Signature-based SER analysis and design of logic circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Improving chip multiprocessor reliability through code replication
Computers and Electrical Engineering
Clock skew scheduling for soft-error-tolerant sequential circuits
Proceedings of the Conference on Design, Automation and Test in Europe
Multiple transient faults in combinational and sequential circuits: a systematic approach
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
A Probabilistic Approach to Diagnose SETs in Sequential Circuits
Journal of Electronic Testing: Theory and Applications
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Due to reduction in device feature size and supply voltage, the sensitivity to radiation induced transient faults (soft errors) of digital systems increases dramatically. Intensive research has been done so far in modeling and analysis of combinational circuit susceptibility to soft errors, while sequential circuits have received much less attention. In this paper, we present an approach for evaluating the susceptibility of sequential circuits to soft errors. The proposed approach uses symbolic modeling based on BDDs/ADDs and probabilistic sequential circuit analysis. The SER evaluation is demonstrated by the set of experimental results, which show that, for most of the benchmarks used, the SER decreases well below a given threshold (10-7 FIT) within ten clock cycles after the hit. The results obtained with the proposed symbolic framework are within 4% average error and up to 11000X faster when compared to HSPICE detailed circuit simulation.