Soft error rate analysis for sequential circuits
Proceedings of the conference on Design, automation and test in Europe
Verification-guided soft error resilience
Proceedings of the conference on Design, automation and test in Europe
A soft error analysis tool for high-speed digital designs
Proceedings of the 2nd international conference on Ubiquitous information management and communication
Adopting the Drowsy Technique for Instruction Caches: A Soft Error Perspective
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Formal modeling and reasoning for reliability analysis
Proceedings of the 47th Design Automation Conference
A Probabilistic Approach to Diagnose SETs in Sequential Circuits
Journal of Electronic Testing: Theory and Applications
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Sequential elements, flip-flops, latches, and memory cells, are the most vulnerable components to soft errors. Since state-of-the-art designs contain millions of bistables, it is not feasible to protect all system bistables using hardening techniques that impose area, performance, and power overhead. A practical approach is to rank system bistables based on their contribution to the overall system vulnerability and protect the most problematic bistables. This analysis is traditionally performed by fault injection and simulation methods which are intractable for large designs and multi-cycle analysis. In this paper, we present an analytical framework to analyze multi-cycle error propagation behavior and then rank system bistables based on their effects on system-level soft error rate. The number of clock cycles required for an error in a bistable to be propagated to system outputs is used to measure the vulnerability of bistables to soft errors.