ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Power minimization in IC design: principles and applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
HEAT: hierarchical energy analysis tool
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Power analysis for sequential circuits at logic level
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
State assignment for FSM low power design
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
K2: an estimator for peak sustainable power of VLSI circuits
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Sequence compaction for probabilistic analysis of finite-state machines
DAC '97 Proceedings of the 34th annual Design Automation Conference
High-level power modeling, estimation, and optimization
DAC '97 Proceedings of the 34th annual Design Automation Conference
Effects of delay models on peak power estimation of VLSI sequential circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Finite state machine decomposition for low power
DAC '98 Proceedings of the 35th annual Design Automation Conference
Computational kernels and their application to sequential power optimization
DAC '98 Proceedings of the 35th annual Design Automation Conference
Kernel-based power optimization of RTL components: exact and approximate extraction algorithms
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Non-stationary effects in trace-driven power analysis
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Symbolic synthesis of clock-gating logic for power optimization of synchronous controllers
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Stochastic sequential machine synthesis with application to constrained sequence generation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Trace-driven steady-state probability estimation in FSMs with application to power estimation
Proceedings of the conference on Design, automation and test in Europe
FSM decomposition by direct circuit manipulation applied to low power design
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Probabilistic Bottom-Up RTL Power Estimation
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
A Probabilistic Method for the Computation of Testability of RTL Constructs
Proceedings of the conference on Design, automation and test in Europe - Volume 1
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Proceedings of the 41st annual Design Automation Conference
Soft error rate analysis for sequential circuits
Proceedings of the conference on Design, automation and test in Europe
Power Estimation Under User-Specified Input Sequences and Programs
Integrated Computer-Aided Engineering
Proceedings of the 45th annual Design Automation Conference
Semicustom design of zigzag power-gated circuits in standard cell elements
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Pulser gating: a clock gating of pulsed-latch circuits
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Efficient algorithms for multilevel power estimation of VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A timing-dependent power estimation framework considering coupling
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design and optimization of power-gated circuits with autonomous data retention
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Sequential algorithm for low-power encoding internal states of finite state machines
Journal of Computer and Systems Sciences International
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Recently developed methods for power estimation have primarily focused on combinational logic. We present a framework for the efficient and accurate estimation of average power dissipation in sequential circuits. Switching activity is the primary cause of power dissipation in CMOS circuits. Accurate switching activity estimation for sequential circuits is considerably more difficult than that for combinational circuits, because the probability of the circuit being in each of its possible states has to be calculated. The Chapman-Kolmogorov equations can be used to compute the exact state probabilities in steady state. However, this method requires the solution of a linear system of equations of size 2/sup N/ where N is the number of flip-flops in the machine. We describe a comprehensive framework for exact and approximate switching activity estimation in a sequential circuit. The basic computation step is the solution of a nonlinear system of equations which is derived directly from a logic realization of the sequential machine. Increasing the number of variables or the number of equations in the system results in increased accuracy. For a wide variety of examples, we show that the approximation scheme is within 1-3% of the exact method, but is orders of magnitude faster for large circuits. Previous sequential switching activity estimation methods can have significantly greater inaccuracies.