Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
IRSIM: an incremental MOS switch-level simulator
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Precomputation-based sequential logic optimization for low power
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Power estimation methods for sequential logic circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
High-density reachability analysis
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Algebric Decision Diagrams and Their Applications
Formal Methods in System Design
Sequential Circuit Design Using Synthesis and Optimization
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Optimization of combinational and sequential logic circuits for low power using precomputation
ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)
Design for Testability of Gated-Clock FSMs
EDTC '96 Proceedings of the 1996 European conference on Design and Test
The Pentium processor-90/100, microarchitecture and low power circuit design
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
Markovian analysis of large finite state machines
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Kernel-based power optimization of RTL components: exact and approximate extraction algorithms
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Logic Synthesis and Verification
Energy-aware design techniques for differential power analysis protection
Proceedings of the 40th annual Design Automation Conference
A Scalable ODC-Based Algorithm for RTL Insertion of Gated Clocks
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Power-aware clock tree planning
Proceedings of the 2004 international symposium on Physical design
Exposing disk layout to compiler for reducing energy consumption of parallel disk based systems
Proceedings of the tenth ACM SIGPLAN symposium on Principles and practice of parallel programming
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Compiler-Directed Energy Optimization for Parallel Disk Based Systems
IEEE Transactions on Parallel and Distributed Systems
Automatic synthesis of clock gating logic with controlled netlist perturbation
Proceedings of the 45th annual Design Automation Conference
A new paradigm for synthesis and propagation of clock gating conditions
Proceedings of the 45th annual Design Automation Conference
Intelligate: Scalable Dynamic Invariant Learning for Power Reduction
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
A novel sequential circuit optimization with clock gating logic
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Behavior-level observability don't-cares and application to low-power behavioral synthesis
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Resurrecting infeasible clock-gating functions
Proceedings of the 46th Annual Design Automation Conference
Logic synthesis for low power using clock gating and rewiring
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Behavior-Level Observability Analysis for Operation Gating in Low-Power Behavioral Synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Enabling concurrent clock and power gating in an industrial design flow
Proceedings of the Conference on Design, Automation and Test in Europe
On applying erroneous clock gating conditions to further cut down power
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Data-driven clock gating for digital filters
PATMOS'09 Proceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Timing Optimization in Sequential Circuit by Exploiting Clock-Gating Logic
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Recent results have shown that dynamic power management is effective in reducing the total power consumption of sequential circuits. In this paper, we propose a bottom-up approach for the automatic extraction and synthesis of dynamic power management circuitry starting from structural logic-level specifications. Our techniques leverage the compact BDD-based representation of Boolean and pseudo-Boolean functions to detect idle conditions where the clock can be stopped without compromising functional correctness. Moreover, symbolic techniques allow accurate probabilistic computations; in particular, they enable the use of non-equiprobable primary input distributions, a key step in the construction of models that match the behavior of real hardware devices with a high degree of fidelity. The results are encouraging, since power savings of up to 34% have been obtained on standard benchmark circuits.