Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
Architecture of the Pentium Microprocessor
IEEE Micro
Dynamic power management of electronic systems
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
System-level power optimization: techniques and tools
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Symbolic synthesis of clock-gating logic for power optimization of synchronous controllers
ACM Transactions on Design Automation of Electronic Systems (TODAES)
System-level power optimization: techniques and tools
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A survey of design techniques for system-level dynamic power management
Readings in hardware/software co-design
A MAC layer power management scheme for efficient energy delay tradeoff in a WLAN
Computer Networks: The International Journal of Computer and Telecommunications Networking
Energy and performance evaluation of lossless file data compression on server systems
SYSTOR '09 Proceedings of SYSTOR 2009: The Israeli Experimental Systems Conference
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This paper describes the implementation of the Pentium processor (73590,815100), referred to as the Pentium processor-90/100 from now on, on a 3.3V, 0.6 micron BiNMOS process. The processor achieves significantly higher performance over the previous generation Pentium processor, with reduced power consumption, and a smaller die area (12.76 mm each side). A symmetric dual processing feature is also supported that provides even greater performance advantages for multithreaded operating systems such as Windows NT. Aggressive frequency targets (100 MHz) were achieved through innovative circuit design techniques. This paper also briefly discusses some of the key technology improvements that enabled such aggressive performance goals to be met.