i486 microprocessor programmer's reference manual
i486 microprocessor programmer's reference manual
An analysis of MIPS and SPARC instruction set utilization on the SPEC benchmarks
ASPLOS IV Proceedings of the fourth international conference on Architectural support for programming languages and operating systems
The Intel386 CPU family—architecture & performance analysis
COMPCON '92 Proceedings of the thirty-seventh international conference on COMPCON
A High-Speed Analog Neural Processor
IEEE Micro
Using branch handling hardware to support profile-driven optimization
MICRO 27 Proceedings of the 27th annual international symposium on Microarchitecture
The effects of predicated execution on branch prediction
MICRO 27 Proceedings of the 27th annual international symposium on Microarchitecture
DAC '94 Proceedings of the 31st annual Design Automation Conference
Compiler transformations for high-performance computing
ACM Computing Surveys (CSUR)
Optimization of instruction fetch mechanisms for high issue rates
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
An analytical model of high performance superscalar-based multiprocessors
PACT '95 Proceedings of the IFIP WG10.3 working conference on Parallel architectures and compilation techniques
Fast message assembly using compact address relations
Proceedings of the 1996 ACM SIGMETRICS international conference on Measurement and modeling of computer systems
Issues in the Design of High Performance SIMD Architectures
IEEE Transactions on Parallel and Distributed Systems
Area and performance tradeoffs in floating-point divide and square-root implementations
ACM Computing Surveys (CSUR)
A persistent rescheduled-page cache for low overhead object code compatibility in VLIW architectures
Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture
Accurate and practical profile-driven compilation using the profile buffer
Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture
Instruction fetch mechanisms for VLIW architectures with compressed encodings
Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture
Compiler-driven cached code compression schemes for embedded ILP processors
Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture
Processor Implementations Using Queues
IEEE Micro
IEEE Micro
IEEE Micro
The Pentium processor-90/100, microarchitecture and low power circuit design
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
DSPxPlore: design space exploration methodology for an embedded DSP core
Proceedings of the 2004 ACM symposium on Applied computing
The QC-2 parallel Queue processor architecture
Journal of Parallel and Distributed Computing
Larrabee: a many-core x86 architecture for visual computing
ACM SIGGRAPH 2008 papers
Compiler Support for Code Size Reduction Using a Queue-Based Processor
Transactions on High-Performance Embedded Architectures and Compilers II
Modular multi-ported SRAM-based memories
Proceedings of the 2014 ACM/SIGDA international symposium on Field-programmable gate arrays
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The techniques of pipelining, superscalar execution, and branch prediction used in the Pentium CPU, which integrates 3.1 million transistors in 0.8- mu m BiCMOS technology, are described. The technology improvements associated with the three most recent microprocessor generations are outlined. The Pentium's compatibility, performance, organization, and development process are also described. The compiler technology developed with the Pentium microprocessor, which includes machine-independent optimizations common to current high-performance compilers, such as inlining, unrolling, and other loop transformations, is reviewed.