Line (block) size choice for CPU cache memories
IEEE Transactions on Computers
Programming the 80286
Performance tradeoffs in cache design
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
Intel386 SX microprocessor programmer's reference manual
Intel386 SX microprocessor programmer's reference manual
Cache evaluation and the impact of workload choice
ISCA '85 Proceedings of the 12th annual international symposium on Computer architecture
ACM Computing Surveys (CSUR)
Integrated predicated and speculative execution in the IMPACT EPIC architecture
Proceedings of the 25th annual international symposium on Computer architecture
The Gmicro/300 32-Bit Microprocessor
IEEE Micro
Architecture of the Pentium Microprocessor
IEEE Micro
Reducing Branch Delay to Zero in Pipelined Processors
IEEE Transactions on Computers
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The author discusses the design goals of the i486 development program, which were to ensure binary compatibility with the 386 microprocessor and the 387 math coprocessor, increase performance by two to three times over a 386/387 processor system at the same clock rate, and extend the IBM PC standard architecture of the 386 CPU with features suitable for minicomputers. A cache integrated into the instruction pipeline lets this 386-compatible processor achieve minicomputer performance levels. The design and performance of the on-chip cache and the instruction pipeline are examined in detail.