The Gmicro/300 32-Bit Microprocessor

Authors:
Takeshi Kitahara;Taizo Satoh
Affiliations:
-;-
Venue:
IEEE Micro
Year:
1990

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Abstract

A high-end microprocessor, the Gmicro/300, based on the TRON architecture specification is described. In contrast to other RISC (reduced-instruction-set-computer) or CISC (complex-instruction-set-computer) chips, it executes an instruction with a memory operand and a register operand in one clock cycle. Separate cache memories improve performance more than 13.8%. The Gmicro/300's pipeline structure, its other one-cycle structures, and the effects of using internal caches are discussed.