The Gmicro/100 32-Bit Microprocessor

Authors:
Toyohiko Yoshida;Toru Shimisu;Shigeo Mizugaki;Junichi Hinata
Affiliations:
-;-;-;-
Venue:
IEEE Micro
Year:
1991

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Abstract

A description is given of the Gmicro/100, a 32-b VLSI microprocessor based on the TRON specification. The Gmicro/100 five-stage pipeline, prejump mechanism, and bitmap manipulation are examined. Performance results are reported. They show that the prejump mechanism, implemented as a hardware solution for the jump problem, executes benchmark programs 16.8% faster on the average. Optimized microinstructions permit bitmap-manipulation instructions to perform two to five times faster than the software loops. The application-specific standard product approach used to implement Gmicro/100 is discussed.