Computer Programming and Architecture: The VAX-11
Computer Programming and Architecture: The VAX-11
Architecture of the Pentium Microprocessor
IEEE Micro
The Power PC 601 Microprocessor
IEEE Micro
A Characterization of Processor Performance in the vax-11/780
ISCA '84 Proceedings of the 11th annual international symposium on Computer architecture
Planning a computer system: Project Stretch
Planning a computer system: Project Stretch
On the design of a register queue based processor architecture (FaRM-rq)
ISPA'03 Proceedings of the 2003 international conference on Parallel and distributed processing and applications
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This survey paper examines two processor-memory interface problems - long latency and low bandwidth, and the use of queues to resolve them. Queues are classified by data type and prefetch strategies. Queue characteristics and parameters are also discussed. The use of queues to support variable length instructions and reduce misalignment problems are presented. Several example architectures are given in historical perspective - from the IBM 7030 (Stretch) to the Motorola/Apple/IBM PowerPC 601. Each application is detailed, giving queue configurations and prefetch strategies along with the design decisions that lead to their final architectures.