On the design of a register queue based processor architecture (FaRM-rq)

Authors:
Ben A. Abderazek;Soichi Shigeta;Tsutomu Yoshinaga;Masahiro Sowa
Affiliations:
Graduate School of Information Systems, The University of Electro-Communications, Chofu-shi, Tokyo, Japan;Graduate School of Information Systems, The University of Electro-Communications, Chofu-shi, Tokyo, Japan;Graduate School of Information Systems, The University of Electro-Communications, Chofu-shi, Tokyo, Japan;Graduate School of Information Systems, The University of Electro-Communications, Chofu-shi, Tokyo, Japan
Venue:
ISPA'03 Proceedings of the 2003 international conference on Parallel and distributed processing and applications
Year:
2003

Citing 7
Cited 1

Stack computers: the new wave

Stack computers: the new wave
Instruction Issue Logic for High-Performance, Interruptible, Multiple Functional Unit, Pipelined Computers

IEEE Transactions on Computers
Data flow on a queue machine

ISCA '85 Proceedings of the 12th annual international symposium on Computer architecture
Allowing for ILP in an embedded Java processor

Proceedings of the 27th annual international symposium on Computer architecture
Processor Architecture: From Dataflow to Superscalar and Beyond

Processor Architecture: From Dataflow to Superscalar and Beyond
Processor Implementations Using Queues

IEEE Micro
Complexity-effective superscalar processors

Complexity-effective superscalar processors

On the design of a dual-execution modes processor: architecture and preliminary evaluation

ISPA'06 Proceedings of the 2006 international conference on Frontiers of High Performance Computing and Networking

Quantified Score

Hi-index	0.00

Visualization

Abstract

We propose in this paper a processor architecture that supports multi instructions set through run time functional assignment algorithm (RUNFA). The above processor, which is named Functional Assignment Register Microprocessor (FaRM-rq) supports queue and register based instruction set architecture and functions into different modes: (1) R-mode (FRM) - when switched for register based instructions support, and (2) Q-mode (FQM) - when switched for Queue based instructions support. The entities share a common data path and may operate independently though not in parallel. In FRM mode, the machine's shared storage unit (SSU) behaves as a conventional register file. However, in FQM mode, the system organizes the SSU access as a first-in-first-out latches, thus accesses concentrate around a small window and the addressing of registers is implicit trough the Queue head and tail pointers. First, we present the novel aspects of the FaRM-rq1 architecture. Then, we give the novel FQM fundamentals and the principles underlying the architecture.