Allowing for ILP in an embedded Java processor
Proceedings of the 27th annual international symposium on Computer architecture
Parallel Queue Processor Architecture Based on Produced Order Computation Model
The Journal of Supercomputing
High-Level Modeling and FPGA Prototyping of Produced Order Parallel Queue Processor Core
The Journal of Supercomputing
On the design of a register queue based processor architecture (FaRM-rq)
ISPA'03 Proceedings of the 2003 international conference on Parallel and distributed processing and applications
An efficient dynamic switching mechanism (DSM) for hybrid processor architecture
EUC'05 Proceedings of the 2005 international conference on Embedded and Ubiquitous Computing
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In this work, we propose a novel dual-execution modes processor, named FunctionalAssignmentRegisterMachine (FaRM), which supports both Queue and Stack execution models in a single and simple processor core. The hardware elements, instruction formats and the major hardware components of the processor are presented in sufficient detail. We also give a preliminary evaluation result of the designed processor. From our preliminary evaluation results, we found that FaRM processor achieves about 65MHz speed and can execute both Queue and Stack execution models correctly. We also found that the novel architecture is implemented without considerable additional hardware when compared with conventional architectures with similar hardware configurations.