Dual-execution mode processor architecture
The Journal of Supercomputing
Dual-execution mode processor architecture for embedded applications
Journal of Mobile Multimedia
On the design of a dual-execution modes processor: architecture and preliminary evaluation
ISPA'06 Proceedings of the 2006 international conference on Frontiers of High Performance Computing and Networking
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Increasing the processor resources usability and boosting processor compatibility and capability to support multi-executions models in a single core are highly needed nowadays to benefit from the recent developments in electronics technology. This work introduces the concept of a dynamic switching mechanism (DSM), which supports multi-instruction set execution models in a single and simple processor core. This is achieved dynamically by execution mode–switching scheme and a sources–results locations computing unit for a novel queue execution model and a well-known stack based execution model. The queue execution model is based on queue computation that uses queue-registers, a circular queue data structure, for operands and results manipulations and assigns queue words according to a single assignment rule. We present the DSM mechanism and we describe its hardware complexity and preliminary evaluation results. We also describe the DSM target architecture.