ACM SIGMETRICS Performance Evaluation Review
ACM SIGARCH Computer Architecture News
Threaded code designs for Forth interpreters
ACM SIGFORTH Newsletter
HOPL-II The second ACM SIGPLAN conference on History of programming languages
Linear logic and permutation stacks—the Forth shall be first
ACM SIGARCH Computer Architecture News - Special issue: panel sessions of the 1991 workshop on multithreaded computers
A whirlwind tour of FORTH resources
ACM SIGPLAN Notices
The marketing of Forth workshop report
FORTH '90 and '91 Proceedings of the second and third annual workshops on Forth
The silicon palimpsest: a programming model for electrically reconfigurable processors
FORTH '90 and '91 Proceedings of the second and third annual workshops on Forth
Efficient large-scale process-oriented parallel simulations
Proceedings of the 30th conference on Winter simulation
A minimal TTL processor for architecture exploration
SAC '94 Proceedings of the 1994 ACM symposium on Applied computing
Adapting Tomasulo's algorithm for bytecode folding based Java processors
ACM SIGARCH Computer Architecture News - Special Issue: PACT 2001 workshops
A formal model of real-time program compilation
Theoretical Computer Science
Optimal Ordered Problem Solver
Machine Learning
On-chip Stack Based Memory Organization for Low Power Embedded Architectures
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Tina: an improbable 3-pin microcontroller
ACM SIGPLAN Notices
Design and Implementation of an Efficient Stack Machine
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
History of programming languages---II
Cache performance impacts for stack machines in embedded systems
SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design
Transient variable caching in Java’s stack-based intermediate representation
Scientific Programming
A new code generation algorithm for 2-offset producer order queue computation model
Computer Languages, Systems and Structures
ACM SIGPLAN Notices
Efficient compilation for queue size constrained queue processors
Parallel Computing
Compiler Support for Code Size Reduction Using a Queue-Based Processor
Transactions on High-Performance Embedded Architectures and Compilers II
Information Sciences: an International Journal
Compiling for Reduced Bit-Width Queue Processors
Journal of Signal Processing Systems
On the design of a register queue based processor architecture (FaRM-rq)
ISPA'03 Proceedings of the 2003 international conference on Parallel and distributed processing and applications
Designing a java microcontroller to specific applications
SBCCI'99 Proceedings of the XIIth conference on Integrated circuits and systems design
Brief announcement: distributed shared memory based on computation migration
Proceedings of the twenty-third annual ACM symposium on Parallelism in algorithms and architectures
Dual-execution mode processor architecture for embedded applications
Journal of Mobile Multimedia
A self-checking hardware journal for a fault-tolerant processor architecture
International Journal of Reconfigurable Computing - Special issue on selected papers from the international workshop on reconfigurable communication-centric systems on chips (ReCoSoC' 2010)
Advantages of java processors in cache performance and power for embedded applications
SAMOS'06 Proceedings of the 6th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
Distributed computing in sensor networks using multi-agent systems and code morphing
ICAISC'12 Proceedings of the 11th international conference on Artificial Intelligence and Soft Computing - Volume Part II
How to efficiently implement dynamic circuit specialization systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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