IBM RISC System/6000 processor architecture
IBM Journal of Research and Development
The Test Access Port and Boundary-Scan Architecture
The Test Access Port and Boundary-Scan Architecture
IBM Single Chip RISC Processor (RSC)
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
The PowerPC 603 microprocessor
Communications of the ACM
Evolution of the PowerPC Architecture
IEEE Micro
Architectural timing verification of CMOS RISC processors
IBM Journal of Research and Development - Special issue: IBM CMOS technology
Cache performance of fast-allocating programs
FPCA '95 Proceedings of the seventh international conference on Functional programming languages and computer architecture
Fast message assembly using compact address relations
Proceedings of the 1996 ACM SIGMETRICS international conference on Measurement and modeling of computer systems
Area and performance tradeoffs in floating-point divide and square-root implementations
ACM Computing Surveys (CSUR)
Processor Implementations Using Queues
IEEE Micro
IEEE Micro
| Hi-index | 0.02 |
The PowerPC 601 microprocessor, the first of a family of processors based on the PowerPC architecture, is described. The general-purpose processor contains a 32-Kb cache and a superscalar machine organization that allows dispatch and execution of up to three instructions each clock cycle. The bus interface and storage control mechanisms can be configured for a wide range of system designs, from low-cost desktop personal computers to high-performance multi-processor systems. The PowerPC architecture, machine organization, chip packaging technology, and performance are discussed.