The IBM RT PC ROMP processor and memory management unit architecture
IBM Systems Journal
801 storage: architecture and programming
ACM Transactions on Computer Systems (TOCS)
IBM RISC System/6000 processor architecture
IBM Journal of Research and Development
Evolution of storage facilities in AIX Version 3 for RISC System/6000 processors
IBM Journal of Research and Development
RISC System/6000 processor architecture
Microprocessors & Microsystems - Special issue on applying and implementing RISC
Reasoning about parallel architectures
Reasoning about parallel architectures
The Power PC 601 Microprocessor
IEEE Micro
ASPLOS I Proceedings of the first international symposium on Architectural support for programming languages and operating systems
Resource allocation in a high clock rate microprocessor
ASPLOS VI Proceedings of the sixth international conference on Architectural support for programming languages and operating systems
Cache sensitive modulo scheduling
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
IEEE Micro
Reducing memory reference energy with opportunistic virtual caching
Proceedings of the 39th Annual International Symposium on Computer Architecture
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The PowerPC is a new RISC architecture derived from IBM's POWER architecture. The changes made to POWER simplify implementations, increase clock rates, enable a higher degree of superscalar execution, extend the architecture to 64 bits, and add multiprocessor support. For compatibility with existing software, the developers retained POWER's basic instruction set, opcode assignments, and programming model.