Memory access buffering in multiprocessors
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
Efficient and correct execution of parallel programs that share memory
ACM Transactions on Programming Languages and Systems (TOPLAS)
High-performance computer architecture (2nd ed.)
High-performance computer architecture (2nd ed.)
MIPS RISC architectures
Reasoning about parallel architectures
Reasoning about parallel architectures
Evolution of the PowerPC Architecture
IEEE Micro
Memory consistency and event ordering in scalable shared-memory multiprocessors
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
A locality sensitive multi-module cache with explicit management
ICS '99 Proceedings of the 13th international conference on Supercomputing
The semantics of power and ARM multiprocessor machine code
Proceedings of the 4th workshop on Declarative aspects of multicore programming
Understanding POWER multiprocessors
Proceedings of the 32nd ACM SIGPLAN conference on Programming language design and implementation
An axiomatic memory model for POWER multiprocessors
CAV'12 Proceedings of the 24th international conference on Computer Aided Verification
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The PowerPC architecture permits aggressive hardware and software implementations that improve performance by hiding the large relative latency of memory accesses. Hardware and software cooperatively determine the behavior of the memory system, using the architecture's provisions for atomicity, coherence, and synchronization of accesses. The design philosophy is to streamline interfaces among components, to limit synchronization delays. For the memory system, the problem is to reduce processor delays during memory accesses. This motivated the development of systems in which useful work can be accomplished during latency periods. While the processor awaits the arrival of a datum, it can often fetch other data, do computations that do not require the awaited datum, and store other data. Such reordering is limited by data dependences among accesses and computation.