Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
Transformation and synthesis of FSMs for low-power gated-clock implementation
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
A method of redundant clocking detection and power reduction at RT level design
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Symbolic synthesis of clock-gating logic for power optimization of synchronous controllers
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Automating RT-level operand isolation to minimize power consumption in datapaths
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Power Aware Design Methodologies
Power Aware Design Methodologies
Proceedings of the 15th international symposium on System Synthesis
Exploring performance tradeoffs for clustered VLIW ASIPs
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Synthesizable HDL generation method for configurable VLIW processors
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Automatic ADL-based operand isolation for embedded processors
Proceedings of the conference on Design, automation and test in Europe: Proceedings
A clock power model to evaluate impact of architectural and technology optimizations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A scalable algorithm for RTL insertion of gated clocks based on ODCs computation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper proposes a low power VLIW processor generation method by automatically extracting non-redundant activation conditions of pipeline registers for clock gating. It is important for the best power reduction by clock gating to create control signals that can completely shut off redundant clock supplies for registers. In order to generate the control signals automatically, the proposed method utilizes high-level architecture information called Micro-Operation Descriptions, which describes a VLIW processor architecture. Exploiting the Micro-Operation Descriptions in a VLIW processor generation process, the proposed method automatically extracts the non-redundant activation conditions that can control clock gating to supply the minimum clocks to the pipeline registers. Using the non-redundant activation condition extraction, the proposed method achieves short calculation time and low area overhead; the proposed method can be applied to VLIW processor generation. Experimental results show that the VLIW processor generated with proposed method achieves power reduction about 60% compared to the non-clock-gated VLIW processor, and about 35% compared to the VLIW processor that is applied clock gating by PowerCompiler with negligible area overhead.