Low-power architectural design methodologies
Low-power architectural design methodologies
Overview of the power minimization techniques employed in the IBM PowerPC 4xx embedded controllers
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Power minimization in IC design: principles and applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Low Power Digital CMOS Design
Guarded evaluation: pushing power management to logic synthesis/design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Logic Synthesis and Verification
Interconnect-aware high-level synthesis for low power
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Clock-tree power optimization based on RTL clock-gating
Proceedings of the 40th annual Design Automation Conference
A Scalable ODC-Based Algorithm for RTL Insertion of Gated Clocks
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Power-aware clock tree planning
Proceedings of the 2004 international symposium on Physical design
RTL Power Optimization with Gate-Level Accuracy
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Bipartitioning and encoding in low-power pipelined circuits
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Automatic ADL-based operand isolation for embedded processors
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Low power synthesizable register files for processor and IP cores
Integration, the VLSI Journal - Special issue: Low-power design techniques
Novel low-overhead operand isolation techniques for low-power datapath synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Interactive presentation: PowerQuest: trace driven data mining for power optimization
Proceedings of the conference on Design, automation and test in Europe
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
A novel sequential circuit optimization with clock gating logic
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Behavior-level observability don't-cares and application to low-power behavioral synthesis
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Low power synthesizable register files for processor and IP cores
Integration, the VLSI Journal - Special issue: Low-power design techniques
A Multi-Shared Register File Structure for VLIW Processors
Journal of Signal Processing Systems
Architecture enhancements for the ADRES coarse-grained reconfigurable array
HiPEAC'08 Proceedings of the 3rd international conference on High performance embedded architectures and compilers
Implementation of an UWB impulse-radio acquisition and despreading algorithm on a low power ASIP
HiPEAC'08 Proceedings of the 3rd international conference on High performance embedded architectures and compilers
Behavior-Level Observability Analysis for Operation Gating in Low-Power Behavioral Synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A low-power ASIP for IEEE 802.15.4a ultra-wideband impulse radio baseband processing
Proceedings of the Conference on Design, Automation and Test in Europe
Timing Optimization in Sequential Circuit by Exploiting Clock-Gating Logic
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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