Precomputation-based sequential logic optimization for low power
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Overview of the power minimization techniques employed in the IBM PowerPC 4xx embedded controllers
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Automating RT-level operand isolation to minimize power consumption in datapaths
DATE '00 Proceedings of the conference on Design, automation and test in Europe
First Level Hold: A Novel Low-Overhead Delay Fault Testing Technique
DFT '04 Proceedings of the Defect and Fault Tolerance in VLSI Systems, 19th IEEE International Symposium
A Novel Low-Power Scan Design Technique Using Supply Gating
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
Guarded evaluation: pushing power management to logic synthesis/design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Models and algorithms for bounds on leakage in CMOS circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Stochastic networked computation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Leveraging rule-based designs for automatic power domain partitioning
Proceedings of the International Conference on Computer-Aided Design
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Power consumption in datapath modules due to redundant switching is an important design concern for high-performance applications. Operand isolation schemes that reduce this redundant switching incur considerable overhead in terms of delay, power, and area. This paper presents novel operand isolation techniques based on supply gating that reduce overheads associated with isolating circuitry. The proposed schemes also target leakage minimization and additional operand isolation at the internal logic of datapath to further reduce power consumption. We integrate the proposed techniques and power/delay models to develop a synthesis flow for low-power datapath synthesis. Simulation results show that the proposed operand isolation techniques achieve at least 40% reduction in power consumption compared to original circuit with minimal area overhead (5%) and delay penalty (0.15%).