Design methodology for fine-grained leakage control in MTCMOS
Proceedings of the 2003 international symposium on Low power electronics and design
Effectiveness and scaling trends of leakage control techniques for sub-130nm CMOS technologies
Proceedings of the 2003 international symposium on Low power electronics and design
Automatic ADL-based operand isolation for embedded processors
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Leakage in Nanometer CMOS Technologies (Series on Integrated Circuits and Systems)
Leakage in Nanometer CMOS Technologies (Series on Integrated Circuits and Systems)
Novel low-overhead operand isolation techniques for low-power datapath synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fine-grained sleep transistor sizing algorithm for leakage power minimization
Proceedings of the 44th annual Design Automation Conference
From WiFi to WiMAX: Techniques for High-Level IP Reuse across Different OFDM Protocols
MEMOCODE '07 Proceedings of the 5th IEEE/ACM International Conference on Formal Methods and Models for Codesign
Proceedings of the conference on Design, automation and test in Europe
Synthesis from multi-cycle atomic actions as a solution to the timing closure problem
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Low Power Methodology Manual: For System-on-Chip Design
Low Power Methodology Manual: For System-on-Chip Design
Power gating: Circuits, design methodologies, and best practice for standard-cell VLSI designs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
What is IEEE P1801 (Unified Power Format)?
ACM SIGDA Newsletter
Airblue: a system for cross-layer wireless protocol development
Proceedings of the 6th ACM/IEEE Symposium on Architectures for Networking and Communications Systems
Low Power Hardware Synthesis from Concurrent Action-Oriented Specifications
Low Power Hardware Synthesis from Concurrent Action-Oriented Specifications
Decoupling for power gating: sources of power noise and design strategies
Proceedings of the 48th Design Automation Conference
A Comparative Evaluation of High-Level Hardware Synthesis Using Reed–Solomon Decoder
IEEE Embedded Systems Letters
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Leakage power reduction through power gating requires considerable design and verification effort. We present a scheme which uses high-level design description to automatically generate a collection of fine-grain power domains and associated control signals. We also describe a method of collecting the dynamic activity characteristics of a domain, viz. total inactivity and frequency of inactive-active transitions, which are necessary to decide the domain's suitability for power gating. Our automated power-gating technique provides power savings without exacerbating the verification problem because the power domains are correct by construction. We illustrate our technique using two wireless decoder designs.