A Comparative Evaluation of High-Level Hardware Synthesis Using Reed–Solomon Decoder

Authors:
A. Agarwal;Man Cheuk Ng; Arvind
Affiliations:
Comput. Sci. & Artificial Intell. Lab. (CSAIL), Massachusetts Inst. of Technol., Cambridge, MA, USA;-;-
Venue:
IEEE Embedded Systems Letters
Year:
2010

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Abstract

Using the example of a Reed-Solomon decoder, we provide insights into what type of hardware structures are needed to be generated to achieve specific performance targets. Due to the presence of run-time dependencies, sometimes it is not clear how the C code can be restructured so that a synthesis tool can infer the desired hardware structure. Such hardware structures are easy to express in an HDL. We present an implementation in Bluespec, a high-level HDL, and show a 7.8× improvement in performance while using only 0.45× area of a C-based implementation.