Fine-grained sleep transistor sizing algorithm for leakage power minimization

Authors:
De-Shiuan Chiou;Da-Cheng Juan;Yu-Ting Chen;Shih-Chieh Chang
Affiliations:
National Tsing Hua University, Hsinchu, Taiwan, R.O.C.;National Tsing Hua University, Hsinchu, Taiwan, R.O.C.;National Tsing Hua University, Hsinchu, Taiwan, R.O.C.;National Tsing Hua University, Hsinchu, Taiwan, R.O.C.
Venue:
Proceedings of the 44th annual Design Automation Conference
Year:
2007

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Abstract

Power gating is one of the most effective ways to reduce leakage power. In this paper, we introduce a new relationship among Maximum Instantaneous Current, IR drops and sleep transistor networks from a temporal viewpoint. Based on this relationship, we propose an algorithm to reduce the total sizes of sleep transistors in Distributed Sleep Transistor Network designs. On average, the proposed method can achieve 21% reduction in the sleep transistor size.