Proceedings of the 39th annual Design Automation Conference
Automated selective multi-threshold design for ultra-low standby applications
Proceedings of the 2002 international symposium on Low power electronics and design
On optimal physical synthesis of sleep transistors
Proceedings of the 2004 international symposium on Physical design
Distributed sleep transistor network for power reduction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Leakage control through fine-grained placement and sizing of sleep transistors
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Challenges in sleep transistor design and implementation in low-power designs
Proceedings of the 43rd annual Design Automation Conference
Proceedings of the 43rd annual Design Automation Conference
Two-phase fine-grain sleep transistor insertion technique in leakage critical circuits
Proceedings of the 2006 international symposium on Low power electronics and design
A Power Network Synthesis Method for Industrial Power Gating Designs
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
Fine-grained sleep transistor sizing algorithm for leakage power minimization
Proceedings of the 44th annual Design Automation Conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Sleep transistor sizing for leakage power minimization considering temporal correlation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Power gating design for standard-cell-like structured ASICs
Proceedings of the Conference on Design, Automation and Test in Europe
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Power Gating is an effective method to reduce leakage power. One of the most important issues in power gating design is the decision on the size of sleep transistor, which is mostly determined by the maximum instantaneous current (MIC) and the maximum tolerable voltage drop. In order to reduce the sleep transistor area, the distributed sleep transistor network (DSTN) was proposed to reduce MIC by connecting all the virtual ground nets together. Most of the following works focused on estimating the MICs through sleep transistors accurately. But the previous works use a pre-defined global voltage drop constraint on circuit, which leads to a uniform gate slowdown. In this paper, we propose a performance driven methodology for DSTN design, which exploits the maximum tolerable voltage drops of gates, particularly the non-critical ones, to reduce the total sleep transistor area without additional performance loss. Moreover, a clustering strategy in placement is proposed to help further reduce the total sleep transistor area. Experimental results show that the proposed approach can reduce the total sleep transistor area by about 36% on average.