Convex separable optimization is not much harder than linear optimization
Journal of the ACM (JACM)
Transistor sizing issues and tool for multi-threshold CMOS technology
DAC '97 Proceedings of the 34th annual Design Automation Conference
MTCMOS hierarchical sizing based on mutual exclusive discharge patterns
DAC '98 Proceedings of the 35th annual Design Automation Conference
Can recursive bisection alone produce routable placements?
Proceedings of the 37th Annual Design Automation Conference
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Distributed sleep transistor network for power reduction
Proceedings of the 40th annual Design Automation Conference
Design methodology for fine-grained leakage control in MTCMOS
Proceedings of the 2003 international symposium on Low power electronics and design
Proceedings of the 2003 international symposium on Low power electronics and design
Sizing and Characterization of Leakage-Control Cells for Layout-Aware Distributed Power-Gating
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Design and optimization of multithreshold CMOS (MTCMOS) circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Simultaneous Fine-grain Sleep Transistor Placement and Sizing for Leakage Optimization
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
A combined gate replacement and input vector control approach for leakage current reduction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Two-phase fine-grain sleep transistor insertion technique in leakage critical circuits
Proceedings of the 2006 international symposium on Low power electronics and design
Sleep transistor distribution in row-based MTCMOS designs
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Design of a family of sleep transistor cells for a clustered power-gating flow in 65nm technology
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Monte-Carlo driven stochastic optimization framework for handling fabrication variability
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Sizing and placement of charge recycling transistors in MTCMOS circuits
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
A novel performance driven power gating based on distributed sleep transistor network
Proceedings of the 18th ACM Great Lakes symposium on VLSI
A scalable algorithmic framework for row-based power-gating
Proceedings of the conference on Design, automation and test in Europe
Two-phase fine-grain sleep transistor insertion technique in leakage critical circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An MTCMOS technology for low-power physical design
Integration, the VLSI Journal
Design of a flexible reactivation cell for safe power-mode transition in power-gated circuits
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Sleep transistor sizing and adaptive control for supply noise minimization considering resonance
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power gating design for standard-cell-like structured ASICs
Proceedings of the Conference on Design, Automation and Test in Europe
Finding the energy efficient curve: gate sizing for minimum power under delay constraints
VLSI Design - Special issue on CAD for Gigascale SoC Design and Verification Solutions
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Genetic algorithm based fine-grain sleep transistor insertion technique for leakage optimization
ICNC'06 Proceedings of the Second international conference on Advances in Natural Computation - Volume Part I
Current density aware power switch placement algorithm for power gating designs
Proceedings of the 2014 on International symposium on physical design
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Leakage power is increasingly gaining importance with technology scaling. Multi-threshold CMOS (MTCMOS) technology has become a popular technique for standby power reduction. Sleep transistor insertion in circuits is an effective application of MTCMOS technology for reducing leakage power. In This work we present a fine grained approach where each gate in the circuit is provided an independent sleep transistor. Key advantages of this approach include better circuit slack utilization and improvements in signal integrity (which is a major disadvantage in clustering based approaches). To this end, we propose an optimal polynomial time fine grained sleep transistor sizing algorithm. We also prove the selective sleep transistor placement problem as NP-complete and propose an effective heuristic. Finally, in order to reduce the sleep transistor area penalty (which might get high since clustering is not performed), we propose a placement area constrained sleep transistor sizing formulation. Our experiments show that on an average the sleep transistor placement and optimal sizing algorithm gave 69.7% and 59.0% savings in leakage power as compared to the conventional fixed delay penalty algorithms for 5 and 7% circuit slowdown respectively. Moreover the post placement area penalty was less than 5% which is comparable to clustering schemes according to Mohab Anis et al. (2003).