Clustered voltage scaling technique for low-power design
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
MTCMOS hierarchical sizing based on mutual exclusive discharge patterns
DAC '98 Proceedings of the 35th annual Design Automation Conference
Automated selective multi-threshold design for ultra-low standby applications
Proceedings of the 2002 international symposium on Low power electronics and design
Distributed sleep transistor network for power reduction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Leakage control through fine-grained placement and sizing of sleep transistors
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Sleep transistor sizing using timing criticality and temporal currents
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Functionality directed clustering for low power MTCMOS design
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Proceedings of the 43rd annual Design Automation Conference
Proceedings of the conference on Design, automation and test in Europe
Timing-driven row-based power gating
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Design and optimization of multithreshold CMOS (MTCMOS) circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Multiple power-gating domain (multi-VGND) architecture for improved leakage power reduction
Proceedings of the 13th international symposium on Low power electronics and design
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
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Leakage power is a serious concern in nanometer CMOS technologies. In this paper we focus on leakage reduction through automatic insertion of sleep transistors for power gating in standard cell based designs. In particular, we propose clustering algorithms for row-based power-gating methodology which is based on using rows of the layout as the granularity for clustering. Our clustering methodology does timing and area constraint driven power-gating in contrast to only timing driven power-gating as proposed in the previous works. We present two distinct clustering algorithms with different accuracy-efficiency trade-off. An optimal one, which exploits a 0--1 or Binary Integer Programming approach, and a heuristic one, which resorts to an implicit enumeration of the layout rows. Results show that, for all the benchmarks, the leakage power savings, as compared to previous techniques, are more than 75% when we have the same timing constraints but half sleep transistor area and at least 60% when area constraint is set at one fourth. We also show that we can perform clustering with no speed degradation and achieve maximum leakage power savings up-to 83%.