Genetic algorithm based fine-grain sleep transistor insertion technique for leakage optimization

Authors:
Yu Wang;Yongpan Liu;Rong Luo;Huazhong Yang
Affiliations:
Department of Electronics Engineering, Tsinghua University, Beijing, P.R. China;Department of Electronics Engineering, Tsinghua University, Beijing, P.R. China;Department of Electronics Engineering, Tsinghua University, Beijing, P.R. China;Department of Electronics Engineering, Tsinghua University, Beijing, P.R. China
Venue:
ICNC'06 Proceedings of the Second international conference on Advances in Natural Computation - Volume Part I
Year:
2006

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Abstract

Fine-grain Sleep Transistor Insertion (FGSTI) is an effective leakage reduction method in VLSI design optimization. In this paper, a novel Genetic Algorithm (GA) based FGSTI technique is presented to decide where to put the sleep transistors (ST) when the circuit slowdown is not enough to assign sleep transistors everywhere in the combinational circuits. Penalty based fitness function with a built-in circuit delay calculator is used to meet the performance constraint. Although optimal FGSTI problem is proved to be NP-hard, our method can steadily give a flexible trade-off between runtime and accuracy. Furthermore a Successive Chromosome Initialization method is proposed to reduce the computation complexity when the circuit slowdown is 3% and 5%. Our experimental results show that the GA based FGSTI technique can achieve about 75%, 94% and 97% leakage current saving when the circuit slowdown is 0%, 3% and 5% respectively.