Introduction to algorithms
MTCMOS hierarchical sizing based on mutual exclusive discharge patterns
DAC '98 Proceedings of the 35th annual Design Automation Conference
Design and optimization of dual-threshold circuits for low-voltage low-power applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A minimum total power methodology for projecting limits on CMOS GSI
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low-power electronics and design
Proceedings of the 39th annual Design Automation Conference
Subthreshold leakage modeling and reduction techniques
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Distributed sleep transistor network for power reduction
Proceedings of the 40th annual Design Automation Conference
VLSID '01 Proceedings of the The 14th International Conference on VLSI Design (VLSID '01)
Proceedings of the 2003 international symposium on Low power electronics and design
Dynamic VTH Scaling Scheme for Active Leakage Power Reduction
Proceedings of the conference on Design, automation and test in Europe
Gate leakage reduction for scaled devices using transistor stacking
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Leakage current reduction in CMOS VLSI circuits by input vector control
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Distributed sleep transistor network for power reduction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Leakage control through fine-grained placement and sizing of sleep transistors
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Simultaneous Fine-grain Sleep Transistor Placement and Sizing for Leakage Optimization
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Discrete Vt assignment and gate sizing using a self-snapping continuous formulation
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Algorithms for minimizing standby power in deep submicrometer, dual-Vt CMOS circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Power optimization with power islands synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Sleep transistor (ST) insertion is a valuable leakage reduction technique in circuit standby mode. Fine-grain sleep transistor insertion (FGSTI) makes it easier to guarantee circuit functionality and improve circuit noise margins. In this paper, we introduce a novel two-phase FGSTI technique which consists of ST placement and ST sizing. These two phases are formally modeled using mixed integer linear programming (MILP) models. When the circuit timing relaxation is not large enough to assign ST everywhere, leakage feedback (LF) gates, which are used to avoid floating states, induce large area and dynamic power overhead. An extended multi-object ST placement model is further proposed to reduce the leakage current and the LF gate number simultaneously. Finally, heuristic algorithms are developed to speed up the ST placement phase. Our experimental results on the ISCAS'85 benchmarks reveal that: 1) the two-phase FGSTI technique achieves better results than the simultaneous ST placement and sizing method; 2) when the circuit timing relaxation varies from 0% to 5%, the multi-object ST placement model can achieve on average 4 ×-9 × LF gate number reduction, while the leakage difference is only about 8% of original circuit leakage; 3) our heuristic algorithm is 1000× faster than the MILP method within an acceptable loss of accuracy.