Characterizing and modeling minimum energy operation for subthreshold circuits
Proceedings of the 2004 international symposium on Low power electronics and design
Low-power circuits and technology for wireless digital systems
IBM Journal of Research and Development
Closing the power gap between ASIC and custom: an ASIC perspective
Proceedings of the 42nd annual Design Automation Conference
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
Optimizing CMOS technology for maximum performance
IBM Journal of Research and Development - Advanced silicon technology
Neural Processor as a Dynamic Power Manager for Digital Systems
MICAI '08 Proceedings of the 7th Mexican International Conference on Artificial Intelligence: Advances in Artificial Intelligence
Two-phase fine-grain sleep transistor insertion technique in leakage critical circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power scalability in a mesh-connected reconfigurable architecture
ACM Transactions on Embedded Computing Systems (TECS)
A study on factors influencing power consumption in multithreaded and multicore CPUs
WSEAS Transactions on Computers
Variability-aware architecture level optimization techniques for robust nanoscale chip design
Computers and Electrical Engineering
| Hi-index | 0.00 |
A circuit design methodology minimizing total power drain of a static complementary metal-oxide-semiconductor (CMOS) random logic network for a prescribed performance, operating temperature range, and short channel threshold voltage rolloff is investigated. Physical, continuous, smooth, and compact "transregional" MOSFET drain current models that consider high-field effects in scaled devices and permit tradeoffs between saturation drive current and subthreshold leakage current are employed to model CMOS circuit performance and power dissipation at low voltages. Transregional models are used in conjunction with physical short channel MOSFET threshold voltage rolloff models and stochastic interconnect distributions to project optimal supply voltages, threshold voltages, and device channel widths minimizing total power dissipated by CMOS logic circuits for each National Technology Roadmap for Semiconductors (NTRS) technology generation. Optimum supply voltage, corresponding to minimum total power dissipation, is projected to scale to 510 mV for the 50-nm 10-GHz CMOS generation in the year 2012. Techniques exploiting datapath parallelism to further scale the supply voltage are shown to offer decreasing reductions in power dissipation with technology scaling.