More wires and fewer LUTs: a design methodology for FPGAs
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Novel dual-gate HEMT utilising multiple split gates
Microelectronic Engineering
The Area-Time Complexity of Binary Multiplication
Journal of the ACM (JACM)
A minimum total power methodology for projecting limits on CMOS GSI
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low-power electronics and design
Unified architecture level energy-efficiency metric
Proceedings of the 12th ACM Great Lakes symposium on VLSI
Energy-delay efficiency of VLSI computations
Proceedings of the 12th ACM Great Lakes symposium on VLSI
Proceedings of the seventh Asia-Pacific conference on Computer systems architecture
CRPIT '02 Proceedings of the seventh Asia-Pacific conference on Computer systems architecture
Towards nanocomputer architecture
CRPIT '02 Proceedings of the seventh Asia-Pacific conference on Computer systems architecture
Proceedings of the 2002 international symposium on Low power electronics and design
How Much Logic Should Go in an FPGA Logic Block?
IEEE Design & Test
STOC '79 Proceedings of the eleventh annual ACM symposium on Theory of computing
Reconfigurable Architectures for General-Purpose Computing
Reconfigurable Architectures for General-Purpose Computing
Computational Aspects of VLSI
Area - Time - Power and Design effort: the basic tradeoffs in Application Specific Systems
ASAP '05 Proceedings of the 2005 IEEE International Conference on Application-Specific Systems, Architecture Processors
Architectural Considerations for Energy Efficiency
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
A low-power reconfigurable logic array based on double-gate transistors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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We analyze power--area--performance trade-offs within a hypothetical mesh-connected reconfigurable architecture. A new analytic model relating area, power, and performance based on a simple VLSI complexity metric, is used to determine the behavior of some computing functions mapped to the platform. Although it might reasonably be expected that entirely local connectivity in the array would impose severe delay overheads, thus making performance--power trade-offs more difficult, it was found that the flexibility of the reconfigurable platform, in which logic and interconnect are (mostly) interchangeable, can result in compact layouts, which tends to offset the impact of the interconnect delay.