Reducing power in high-performance microprocessors
DAC '98 Proceedings of the 35th annual Design Automation Conference
Energy-driven integrated hardware-software optimizations using SimplePower
Proceedings of the 27th annual international symposium on Computer architecture
Optimization of high-performance superscalar architectures for energy efficiency
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Inherently Lower-Power High-Performance Superscalar Architectures
IEEE Transactions on Computers
A low-leakage dynamic multi-ported register file in 0.13mm CMOS
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Energy efficient CMOS microprocessor design
HICSS '95 Proceedings of the 28th Hawaii International Conference on System Sciences
Proceedings of the 2002 international symposium on Low power electronics and design
Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
An innovative low-power high-performance programmable signal processor for digital communications
IBM Journal of Research and Development
Balancing hardware intensity in microprocessor pipelines
IBM Journal of Research and Development
A flexible simulation framework for graphics architectures
Proceedings of the ACM SIGGRAPH/EUROGRAPHICS conference on Graphics hardware
Cell Processor Low-Power Design Methodology
IEEE Micro
Tile size selection for low-power tile-based architectures
Proceedings of the 3rd conference on Computing frontiers
Transactions on High-Performance Embedded Architectures and Compilers I
Power scalability in a mesh-connected reconfigurable architecture
ACM Transactions on Embedded Computing Systems (TECS)
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The development of power-efficient microprocessors presents the need to consider power consumption at early stages of design, particularly at the ISA and microarchitecture definition stages, where the potential for power savings is more significant than at lower-level stages, and the opportunity for making power-performance tradeoffs is the largest. Design modifications to the ISA and microarchitecture, however, affect most (if not all) parameters of the design, including architectural speed, code density, clocking rate and power. A reliable metric is required to make knowledgeable power-performance tradeoffs in this multi-dimensional space. This paper derives a unified energy-efficiency metric for evaluating ISA and microarchitecture features, which subsumes other commonly used power-performance metrics as special cases of a more general equation. This new metric is derived based on an analysis of a multi-dimensional power optimization problem, and the resulting formula involves only relative changes in the characteristics of a processor, enabling its application at the early stages of the design.