Technology decomposition and mapping targeting low power dissipation
DAC '93 Proceedings of the 30th international Design Automation Conference
Surveys in combinatorics, 1993
Surveys in combinatorics, 1993
Instruction level power analysis and optimization of software
Journal of VLSI Signal Processing Systems - Special issue on technologies for wireless computing
Dynamic power management of electronic systems
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Lowering power consumption in clock by using globally asynchronous locally synchronous design style
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Non-stationary effects in trace-driven power analysis
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
An architectural solution for the inductive noise problem due to clock-gating
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Journal of VLSI Signal Processing Systems - Special issue on system level design
System-level power optimization: techniques and tools
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Macro-driven circuit design methodology for high-performance datapaths
Proceedings of the 37th Annual Design Automation Conference
Wattch: a framework for architectural-level power analysis and optimizations
Proceedings of the 27th annual international symposium on Computer architecture
New clock-gating techniques for low-power flip-flops
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Profile-driven code execution for low power dissipation (poster session)
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
ACM Transactions on Computer Systems (TOCS)
A static power model for architects
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture
Maximum current estimation considering power gating
Proceedings of the 2001 international symposium on Physical design
Power reduction through work reuse
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Current consumption dynamics at instruction and program level for a VLIW DSP processor
Proceedings of the 14th international symposium on Systems synthesis
Unified architecture level energy-efficiency metric
Proceedings of the 12th ACM Great Lakes symposium on VLSI
Logic Synthesis and Verification
An integrated approach to reducing power dissipation in memory hierarchies
CASES '02 Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems
On achieving balanced power consumption in software pipelined loops
CASES '02 Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems
Analysis of substrate thermal gradient effects on optimal buffer insertion
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Application-driven processor design exploration for power-performance trade-off analysis
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Power-delay modeling of dynamic CMOS gates for circuit optimization
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
IC power distribution challenges
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
On-chip decoupling capacitor optimization using architectural level prediction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Methodical Low-Power ASIP Design Space Exploration
Journal of VLSI Signal Processing Systems
Runtime Reconfiguration Techniques for Efficient General-Purpose Computation
IEEE Design & Test
The Challenges of Wearable Computing: Part 1
IEEE Micro
Ramp Up/Down Functional Unit to Reduce Step Power
PACS '00 Proceedings of the First International Workshop on Power-Aware Computer Systems-Revised Papers
Optimizing Static Power Dissipation by Functional Units in Superscalar Processors
CC '02 Proceedings of the 11th International Conference on Compiler Construction
Energy reduction techniques for multimedia applications with tolerance to deadline misses
Proceedings of the 40th annual Design Automation Conference
Power-efficient issue queue design
Power aware computing
A Power Perspective of Value Speculation for Superscalar Microprocessors
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Instruction Prediction for Step Power Reduction
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Microarchitecture level power and thermal simulation considering temperature dependent leakage model
Proceedings of the 2003 international symposium on Low power electronics and design
A critical analysis of application-adaptive multiple clock processors
Proceedings of the 2003 international symposium on Low power electronics and design
Speculating to reduce unnecessary power consumption
ACM Transactions on Embedded Computing Systems (TECS)
Micro-operation cache: a power aware frontend for variable instruction length ISA
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
Power modeling and reduction of VLIW processors
Compilers and operating systems for low power
Power-aware clock tree planning
Proceedings of the 2004 international symposium on Physical design
Optimal partitioning of globally asychronous locally synchronous processor arrays
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Improved clock-gating through transparent pipelining
Proceedings of the 2004 international symposium on Low power electronics and design
Execution cache-based microarchitecture power-efficient superscalar processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 42nd annual Design Automation Conference
Algorithmic problems in power management
ACM SIGACT News
Power and thermal effects of SRAM vs. Latch-Mux design styles and clock gating choices
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
A sink-n-hoist framework for leakage power reduction
Proceedings of the 5th ACM international conference on Embedded software
Reducing latencies of pipelined cache accesses through set prediction
Proceedings of the 19th annual international conference on Supercomputing
Optimizing the Thermal Behavior of Subarrayed Data Caches
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Compilers for leakage power reduction
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Power-aware scheduling for makespan and flow
Proceedings of the eighteenth annual ACM symposium on Parallelism in algorithms and architectures
Thermal via allocation for 3D ICs considering temporally and spatially variant thermal power
Proceedings of the 2006 international symposium on Low power electronics and design
Speed scaling to manage energy and temperature
Journal of the ACM (JACM)
Simultaneous power and thermal integrity driven via stapling in 3D ICs
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Compilation for compact power-gating controls
ACM Transactions on Design Automation of Electronic Systems (TODAES)
MOUSETRAP: high-speed transition-signaling asynchronous pipelines
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The QC-2 parallel Queue processor architecture
Journal of Parallel and Distributed Computing
Dual-execution mode processor architecture
The Journal of Supercomputing
Power grid analysis benchmarks
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Collaborative sensing of on-chip wire temperatures using interconnect based ring oscillators
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Analog Integrated Circuits and Signal Processing
Activity-sensitive flip-flop and latch selection for reduced energy
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Finding Stress Patterns in Microprocessor Workloads
HiPEAC '09 Proceedings of the 4th International Conference on High Performance Embedded Architectures and Compilers
Power-Efficient Reconfiguration Control in Coarse-Grained Dynamically Reconfigurable Architectures
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Allocating power ground vias in 3D ICs for simultaneous power and thermal integrity
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Complexity Effective Bypass Networks
Transactions on High-Performance Embedded Architectures and Compilers II
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A GALS many-core heterogeneous DSP platform with source-synchronous on-chip interconnection network
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Power-aware scheduling for makespan and flow
Journal of Scheduling
Challenges and methodologies for efficient power budgeting across the die
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Efficient calibration of thermal models based on application behavior
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
A reconfigurable source-synchronous on-chip network for GALS many-core platforms
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special issue on the 2009 ACM/IEEE international symposium on networks-on-chip
An overview of achieving energy efficiency in on-chip networks
International Journal of Communication Networks and Distributed Systems
Exploiting narrow-width values for thermal-aware register file designs
Proceedings of the Conference on Design, Automation and Test in Europe
Power aware SID-based simulator for embedded multicore DSP subsystems
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Thermally optimal stop-go scheduling of task graphs with real-time constraints
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Non-Instruction Fetch-Based Architecture Reduces Almost 100 Percent of the Dynamic Power and Energy
GREENCOM-CPSCOM '10 Proceedings of the 2010 IEEE/ACM Int'l Conference on Green Computing and Communications & Int'l Conference on Cyber, Physical and Social Computing
Obstacle-aware clock-tree shaping during placement
Proceedings of the 2011 international symposium on Physical design
Thermal via allocation for 3-D ICs considering temporally and spatially variant thermal power
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Speed scaling to manage temperature
STACS'05 Proceedings of the 22nd annual conference on Theoretical Aspects of Computer Science
Compiler analysis and supports for leakage power reduction on microprocessors
LCPC'02 Proceedings of the 15th international conference on Languages and Compilers for Parallel Computing
Single FU bypass networks for high clock rate superscalar processors
HiPC'04 Proceedings of the 11th international conference on High Performance Computing
Coupled power and thermal simulation with active cooling
PACS'03 Proceedings of the Third international conference on Power - Aware Computer Systems
Finding extreme behaviors in microprocessor workloads
Transactions on High-Performance Embedded Architectures and Compilers IV
Power devil: tool for power gating strategy selection
Proceedings of the 10th Workshop on Optimizations for DSP and Embedded Systems
Performance-driven dynamic thermal management of MPSoC based on task rescheduling
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Worst-case guarantees on a processor with temperature-based feedback control of speed
ACM Transactions on Embedded Computing Systems (TECS)
| Hi-index | 0.00 |
Power consumption has become one of the biggest challenges in high-performance microprocessor design. The rapid increase in the complexity and speed of each new CPU generation is outstripping the benefits of voltage reduction and feature size scaling. Designers are thus continuously challenged to come up with innovative ways to reduce power, while trying to meet all the other constraints imposed on the design. This paper presents an overview of the issues related to power consumption in the context of Intel CPUs. The main trends that are driving the increased focus on design for low power are described. System and benchmarking issues, and sources of power consumption in a high-performance CPU are briefly described. Techniques that have been tried on real designs in the past are described. The role of CAD tools and their limitations in this domain will also be discussed. In addition, areas that need increased research focus in the future are also pointed out.