An infeasible interior-point algorithm for solving primal and dual geometric programs
Mathematical Programming: Series A and B - Special issue: interior point methods in theory and practice
Reducing power in high-performance microprocessors
DAC '98 Proceedings of the 35th annual Design Automation Conference
Gradient-based optimization of custom circuits using a static-timing formulation
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
Gate sizing in MOS digital circuits with linear programming
EURO-DAC '90 Proceedings of the conference on European design automation
Timing and area optimization for standard-cell VLSI circuit design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Datapath design is one of the most critical elements in the design of a high performance microprocessor. However datapath design is typically does manually, and is often custom style. This adversely impacts the overall productivity of the design team, as well as the quality of the design. In spite of this, very little automation has been available to the designers of high performance datapaths. In this paper we present a new “macro-driven” approach to the design of datapath circuits. Our approach, referred to as SMART (Smart Macro Design Advisor), is based on automatic generation of regular datapath components such as muxes, comparators, adders etc., which we refer to as datapath macros. The generated solution is based on designer provided constraints such as delay, load and slope, and is optimized for a designer provided cost metric such as power, area. Results on datapath circuits of a high-performance microprocessor show that this approach is very effective for both designer productivity as well as design quality.